Digital System Design using Field Programable Gate Arrays
FPGAs typically run at much slower clock speeds than the latest CPUs, yet they can more than make up for this with their superior memory bandwidth, high degree of parallelization, and the customization that is possible. There is currently a tremendous amount of attention in FPGAs.
If we compare the cost of creating an FPGA design, it is much lower than that for an ASIC or ASSP. At the same time, implementing design changes is much easier in FPGAs and the time-to-market for such designs is much faster.
Digital designs once built in custom silicon are increasingly implemented in field programmable gate arrays (FPGAs). Effective FPGA system design requires a strong understanding of design issues and constraints, and an understanding of the latest FPGA-specific techniques.
At the end of the course student can understand the FPGA based system design, solve a real-world problems and map and port these problems in an FPGA board.
Students Get Hands-On Experience of State of the art tools and technologies
1) FPGA Architecture and Implementation
2) System Design using 65 nm and 28 nm FPGA technology
3) Hardware Design Methodology – Register Transfer Level Design using VHDL/Verilog
4) Static Timing and Power Analysis
5) Simulation on modelsim
6) EDA Tool flow: (Xilinx Vivado, Altera Quartus, Syplicity Tool)
7) System on Chip (Zynq-7000 line of 28 nm SoC devices and Altera DE1 Soc dual-core Cortex-A9)
If we compare the cost of creating an FPGA design, it is much lower than that for an ASIC or ASSP. At the same time, implementing design changes is much easier in FPGAs and the time-to-market for such designs is much faster.
Digital designs once built in custom silicon are increasingly implemented in field programmable gate arrays (FPGAs). Effective FPGA system design requires a strong understanding of design issues and constraints, and an understanding of the latest FPGA-specific techniques.
At the end of the course student can understand the FPGA based system design, solve a real-world problems and map and port these problems in an FPGA board.
Students Get Hands-On Experience of State of the art tools and technologies
1) FPGA Architecture and Implementation2) System Design using 65 nm and 28 nm FPGA technology
3) Hardware Design Methodology – Register Transfer Level Design using VHDL/Verilog
4) Static Timing and Power Analysis
5) Simulation on modelsim
6) EDA Tool flow: (Xilinx Vivado, Altera Quartus, Syplicity Tool)
7) System on Chip (Zynq-7000 line of 28 nm SoC devices and Altera DE1 Soc dual-core Cortex-A9)
UCERD Rawalpindi
Supercomputing Center
UCERD Murree
Lec 1) Introduction to Digital System Design
Lec 2) Introduction to FPGAs
Lec 3) Verilog HDL I
Lec3) Verilog HDL II
Lec 3) Verilog HDL III
Lec 4) Digital Systems and Design Metholodogy
Lec 5) Verilog (Procedural Statements)
Lec 6) Verilog (Expressing Sequential Circuits and FSM)
Lec 7) Verilog (Expressing FSM in Verilog (contd) and FSM State Encoding)
Lec 8) Circuit Timing
Lec 9) Metastability
Lec 10) Arithmetic Circuits
Lec 10) Number System
Lec 11) ASM and Micorprogrammd SM
Lec 12) High Level Synthesis
Lec 13) Dynamic Partial Reconfiguration
Lec 14) Power
Lec 2) Introduction to FPGAs
Lec 3) Verilog HDL I
Lec3) Verilog HDL II
Lec 3) Verilog HDL III
Lec 4) Digital Systems and Design Metholodogy
Lec 5) Verilog (Procedural Statements)
Lec 6) Verilog (Expressing Sequential Circuits and FSM)
Lec 7) Verilog (Expressing FSM in Verilog (contd) and FSM State Encoding)
Lec 8) Circuit Timing
Lec 9) Metastability
Lec 10) Arithmetic Circuits
Lec 10) Number System
Lec 11) ASM and Micorprogrammd SM
Lec 12) High Level Synthesis
Lec 13) Dynamic Partial Reconfiguration
Lec 14) Power
Source code: Verilog Examples
Fundamentals of Digital Logic with Verilog Design
How to make RISC-V Microcomputer using FPGA for programmer
FPGA Programming for Beginners
Computer Architecture Tutorial Using an FPGA: ARM & Verilog Introductions
FPGA-BASED Hardware Accelerators
Digital Logic: With an Introduction to Verilog and FPGA-Based Design
Hands-on Experience with Altera FPGA Development Boards
Verilog:
First time Verilog’ers, must read:
Stephen Brown: Fundamentals of Digital Logic with Verilog
o 2.10
o Appendix-A: Verilog Reference
Advanced users may consult Chapter-2 from Dr. Shoaib’s book.
Beginners must read class lecture slides and above Stephen Brown reference before reading
Chapter-2 from Dr. Shoaib’s book.
Verification Productivity Gap: [see
http://ieeexplore.ieee.org/document/6691175/]
• We briefly discussed that FPGA Routing and Placement tend to be slow and
there are recent efforts to parallelize these steps through GPU. Take a look at
this paper: [http://dl.acm.org/citation.cfm?id=3021732] downloadable when
connected from SEECS. Also see the presentation here:
http://isfpga.org/slides/D2_S2_03.pdf
• For people curious about the internals of FPGA Routing circuitry i.e Switch-block,
see this thesis: http://www.ece.ubc.ca/~stevew/papers/pdf/imran_masc.pdf
Though pretty old but still highlights the routing challenges very well.
• Yet another good read on FPGA architecture and CAD. See LMS, second week
lectures corner. Highly recommended.
Fundamentals of Digital Logic with Verilog Design
How to make RISC-V Microcomputer using FPGA for programmer
FPGA Programming for Beginners
Computer Architecture Tutorial Using an FPGA: ARM & Verilog Introductions
FPGA-BASED Hardware Accelerators
Digital Logic: With an Introduction to Verilog and FPGA-Based Design
Hands-on Experience with Altera FPGA Development Boards
Verilog:
First time Verilog’ers, must read:
Stephen Brown: Fundamentals of Digital Logic with Verilog
o 2.10
o Appendix-A: Verilog Reference
Advanced users may consult Chapter-2 from Dr. Shoaib’s book.
Beginners must read class lecture slides and above Stephen Brown reference before reading
Chapter-2 from Dr. Shoaib’s book.
Verification Productivity Gap: [see
http://ieeexplore.ieee.org/document/6691175/]
• We briefly discussed that FPGA Routing and Placement tend to be slow and
there are recent efforts to parallelize these steps through GPU. Take a look at
this paper: [http://dl.acm.org/citation.cfm?id=3021732] downloadable when
connected from SEECS. Also see the presentation here:
http://isfpga.org/slides/D2_S2_03.pdf
• For people curious about the internals of FPGA Routing circuitry i.e Switch-block,
see this thesis: http://www.ece.ubc.ca/~stevew/papers/pdf/imran_masc.pdf
Though pretty old but still highlights the routing challenges very well.
• Yet another good read on FPGA architecture and CAD. See LMS, second week
lectures corner. Highly recommended.
Dr. Tassadaq Hussain.
He is a permanent faculty member at, Riphah International University.
He did his Ph.D. from Barcelona-tech Spain, in collaboration with Barcelona Supercomputing Center and Microsoft Research Center.
He is a member of HiPEAC: European Network on High Performance and Embedded Architecture and Compilation, Barcelona Supercomputing Center and Microsoft ResearchCentre Spain.
Until January 2018, he had more than 14 years of industrial experience including, Barcelona Supercomputing Centre Spain, Infineon technology France, Microsoft Research Cambridge, PLDA Italia, IBM Zurich Switzerland, and REPSOL Spain. He has published more than 50 international publications and filed 5 patents.
Tassadaq's main research lines are Machine Learning, Parallel Programming, Heterogeneous Multi-core Architectures, Single board Computers, Embedded Computer Vision, Runtime Resource Aware Architectures, Software Defined Radio and Supercomputing for Artificial Intelligence and Scientific Computing.
www.tassadaq.ucerd.com
He is a permanent faculty member at, Riphah International University.
He did his Ph.D. from Barcelona-tech Spain, in collaboration with Barcelona Supercomputing Center and Microsoft Research Center.
He is a member of HiPEAC: European Network on High Performance and Embedded Architecture and Compilation, Barcelona Supercomputing Center and Microsoft ResearchCentre Spain.
Until January 2018, he had more than 14 years of industrial experience including, Barcelona Supercomputing Centre Spain, Infineon technology France, Microsoft Research Cambridge, PLDA Italia, IBM Zurich Switzerland, and REPSOL Spain. He has published more than 50 international publications and filed 5 patents.
Tassadaq's main research lines are Machine Learning, Parallel Programming, Heterogeneous Multi-core Architectures, Single board Computers, Embedded Computer Vision, Runtime Resource Aware Architectures, Software Defined Radio and Supercomputing for Artificial Intelligence and Scientific Computing.
www.tassadaq.ucerd.com
RI
SC-V based System on Chip Architecture on FPGADeveloping an Accelerator for RISC-V System on Chip
Memory Controller for RISC-V Processor
Vector Processor Architecture
FPGA based Accelerators
HDL for Converting 2D Motion Pictures to 3D
Real-time feature-based video stabilization on FPGA
UCERD Gathering Intellectuals Fostering Innovations
Unal Center of Educaiton Research & Development
Unal Center of Educaiton Research & Development
