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AMC: Advanced Multi-accelerator Controller

AMC: Advanced Multi-accelerator Controller

Nov 4, 2014

AMC: Advanced Multi-accelerator Controller

  • a Barcelona Supercomputing Center, Barcelona, Spain
  • b Microsoft Research, Barcelona, Spain
  • c Unal Center of Engineering Research & Development, Barcelona, Spain

Highlights

•     In this article, we propose AMC an intelligent memory system and efficient scheduler.
•     The AMC can operates without intervention of master core or Operating system.
•     It supports multi-accelerators designed by High Level Synthesis tools.
•     The system is evaluated with memory intensive accelerators tested on a Xilinx ML505 evaluation FPGA board.
•     Results show that the AMC system achieves 10.4x and 7x of speed-up compared to generic HLS multi-accelerator systems.

Abstract

The rapid advancement, use of diverse architectural features and introduction of High Level Synthesis (HLS) tools in FPGA technology have enhanced the capacity of data-level parallelism on a chip. A generic FPGA based HLS multi-accelerator system requires a microprocessor (master core) that manages memory and schedules accelerators. In a real environment, such HLS multi-accelerator systems do not give a perfect performance due to memory bandwidth issues. Thus, a system demands a memory manager and a scheduler that improves performance by managing and scheduling the multi-accelerator’s memory access patterns efficiently. In this article, we propose the integration of an intelligent memory system and efficient scheduler in the HLS-based multi-accelerator environment called Advanced Multi-accelerator Controller (AMC). The AMC system is evaluated with memory intensive accelerators, High Performance Computing (HPC) applications and implemented and tested on a Xilinx Virtex-5 ML505 evaluation FPGA board. The performance of the system is compared against the microprocessor-based systems that have been integrated with the operating system. Results show that the AMC based HLS multi-accelerator system achieves 10.4x and 7x of speedup compared to the MicroBlaze and Intel Core based HLS multi-accelerator systems.

 

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PGC: Programmable Graphics Controller

PGC: Programmable Graphics Controller

Oct 30, 2014

PGC: Programmable Graphics Controller

Authors: Tassadaq Hussain, Amna Haider

Publication date: 2014/4
Book: Appeared in HiPEAC Info: NETWORK OF EXCELLENCE ON HIGH PERFORMANCE AND EMBEDDED ARCHITECTURE AND COMPILATION

issue 38

PGC HiPEACPublisher: HiPEAC

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Stand-alone Memory Controller for Graphics System

Stand-alone Memory Controller for Graphics System

Oct 30, 2014

Authors: Tassadaq Hussain, Oscar Palomar, Adrian Cristal, Osman Unsal, Eduard Ayguade, Mateo Valero, Amna Haider
Publication date: 2014/4
Conference: The 10th International Symposium on Applied Reconfigurable Computing (ARC 2014) (28% Acceptance Rate for Full Paper)

 

Publisher: ACM
Description
Abstract There has been a dramatic increase in the complexity of graphics applications in
System-on-Chip (SoC) with a corresponding increase in performance requirements. Various
powerful and expensive platforms to support graphical applications appeared recently. All
these platforms require a high performance core that manages and schedules the high
speed data of graphics peripherals (camera, display, etc.) and an efficient on chip scheduler.
In this article we design and propose a SoC based Programmable Graphics Controller (
PGC: A Programmable Graphics Controller

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PMSS: A programmable memory system and scheduler for complex memory patterns

Authors: Tassadaq Hussain, Amna Haider and Eduard Ayguade
Publication date: 2014
Journal: Journal of Parallel and Distributed Computing

Description:

Abstract HPC industry demands more computing units on FPGAs, to enhance the
performance by using task/data parallelism. FPGAs can provide its ultimate performance on
certain kernels by customizing the hardware for the applications. However, applications are
getting more complex, with multiple kernels and complex data arrangements, generating
overhead while scheduling/managing system resources. Due to this reason all classes of
multi threaded machines–minicomputer to supercomputer–require to have efficient

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PGC: a pattern-based graphics controller

PGC: a pattern-based graphics controller

Oct 30, 2014

Authors: Tassadaq Hussain and Amna Haider
Publication date: 2014
Journal: International Journal of Circuits and Architecture Design
Volume 1
Issue 2

Publisher: International Journal of Circuits and Architecture

PGC: A Programmable Graphics Controller
Description
In last decade graphics system have shown a great impact in our lives not only as a
commodity itself but also for specialised use. Various powerful and expensive platforms to
support graphical applications appeared in recent years. All these platforms require a high
performance core that manages and schedules the high speed data of graphics peripherals.
In this article, we design and propose a pattern–based graphics controller (PGC) that
handles graphics peripherals efficiently. The proposed system is highly reliable in terms of

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Programmable Memory Controller for Vector System-on-Chip

Programmable Memory Controller for Vector System-on-Chip

Oct 30, 2014

Author: Tassadaq Hussain

Publication date: 2012

Source: The seventh Microsoft Research Summer School, Microsoft Research in Cambridge, U.K

 

Programmable Memory Controller for Vector System-on-Chip

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Harris extraction and SIFT matching for correlation of two Tablets

Harris extraction and SIFT matching for correlation of two Tablets

Oct 30, 2014

Harris extraction and SIFT matching for correlation of two Tablets

Authors: A Ali, A Georges, Tassadaq Hussain, S Ali
Publisher: World Academy of Science, Engineering and Technology WASET 2011 76 (76), 102-106

tcct

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PPMC : A Programmable Pattern based Memory Controller.

PPMC : A Programmable Pattern based Memory Controller.

Jan 4, 2013

Authors: Hussain Tassadaq,Muhammad Shafiq, Miquel Pericas, Nacho Navarro, Eduard Ayguade.
ARC 2012, the 8th International Symposium on Applied Reconfigurable Computing (2012).

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One of the main challenges in the design of hardware accelerators is the efficient access of data from the external memory. Improving and optimizing the functionality of the memory controller between the external memory and the accelerators is therefore critical. In this paper, we advance toward this goal by proposing PPMC, the Programmable Pattern-based Memory Controller. This controller supports scatter-gather and strided 1D, 2D and 3D accesses with programmable tiling. Compared to existing solutions, the proposed system provides better performance, simplifies programming access patterns and eases software integration by interfacing to high-level programming languages. In addition, the controller offers an interface for automating domain decomposition via tiling. We implemented and tested PPMC on a Xilinx ML505 evaluation board using a MicroBlaze soft-core as the host processor. The evaluation uses six memory intensive application kernels: Laplacian solver, FIR, FFT, Thresholding, Matrix Multiplication, and 3D-Stencil. The results show that the PPMC-enhanced system achieves at least 10x speed-ups for 1D, 2D and 3D memory accesses as compared to a non-PPMC based setup.

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