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Streaming Scatter Gather DMA Controller for Hardware Accelerators

Streaming Scatter Gather DMA Controller for Hardware Accelerators

Jan 4, 2013

Authors Hussain Tassadaq, Miquel Pericas, Nacho Navarro, Eduard Ayguade.
Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2010), Terrassa, July 2010.

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Abstract:

Feeding data to hardware accelerators is an intricate process that affects performance and efficiency of systems. In System-on-chip environments hardware accelerators act as target/slave and movement of data to/from memory is controlled by microprocessor (initiator/master) unit. Processors play middle role they read data from the hardware accelerator and write it to memory and vise versa. This technique provides flexibility but affects the performance of the system. To get maximum benefit from parallelism, HPC applications need to adopt memory controllers that have intelligence like CPU and have potential to synchronize with hardware accelerator. In this abstract we present a memory controller that provides Scatter/Gather DMA functionality. This memory controller takes maximum benefit of the hardware fabric by feeding data in streaming format. Memory access patterns are defined by programmable descriptor blocks available in the controller. We measure gate-count and speed by executing memory controller over Xilinx Virtex 5
ML505 board and compare results with SoC designed in Xilinx base system builder.

KEYWORDS: Master, Slave, FPGA, SoC, HPC Applications

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4 comments

  1. Rzxie /

    I’m interested in the document, however it seems the file is corrupted :(.

  2. cheema /

    Apology for broken link.
    Now link is active.
    Best Regards

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